ASIC VERIFICATION ENGINEER

ASIC Verification Engineer

Key Responsibilities

• Lead and manage the end-to-end verification process for complex SoC (System-on-Chip) designs, ensuring compliance with functional specifications and industry standards.
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• Collaborate closely with design, architecture, and validation teams to define verification strategies and ensure seamless integration across functional blocks.
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• Develop comprehensive test plans and implement constrained-random, coverage-driven verification environments using SystemVerilog and UVM methodology.
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• Create and maintain automation scripts (e.g., Python, Perl, or TCL) to streamline regression execution, log analysis, and coverage reporting.
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• Drive functional and code coverage closure through metric tracking, gap analysis, and targeted test development.
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• Debug complex design and testbench issues in SoC environments, performing waveform analysis and root-cause investigations.
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• Mentor junior engineers on verification best practices, UVM testbench architecture, and debug methodologies.
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• Coordinate activities and maintain effective communication between onsite and offshore verification teams to ensure timely delivery.

Technical Skills & Tools

• Verification Languages: SystemVerilog, UVM, Assertions (SVA)
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• Coverage: Functional coverage, code coverage, coverage closure strategies
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• Automation & Scripting: Python, Perl, Shell/TCL scripting for regression automation and productivity tools
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• Simulation & Debug Tools: VCS, Questa, Verdi, DVE, SimVision
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• Protocols: (Preferred) ARM processors, CHI interconnects, PCIe, DDR, AMBA (AXI/AHB/APB)
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• Version Control & CI/CD: Git, Jenkins, regression dashboard integration
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• EDA Tools: Synopsys, Cadence, Mentor Graphics suites

Preferred Experience

• Exposure to ARM processor subsystems and CHI protocols.
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• Hands-on verification experience with PCIe or DDR interfaces.
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• Familiarity with low-power verification, clock/power domain crossing checks, and formal verification.